# Pipelining: timing and speedup: GATE CS question with solution

From the GATE Daily set of 26 October 2026, question 5 of 10 (https://gatedaily.in/q/2026-10-26-split-ex-stage-new-bottleneck-speedup/). Difficulty: standard.

### Q.5 · Computer Organization & Architecture · Pipelining: timing and speedup · NAT, 2 marks (answer with a number)

A processor's instruction execution is divided into five stages with these delays:

| Stage | IF | ID | EX | MEM | WB |
|---|---|---|---|---|---|
| Delay (ps) | 200 | 150 | 380 | 290 | 120 |

In the pipelined implementation each stage is followed by a pipeline register whose delay of 20 ps adds to the clock period. A designer splits EX into two consecutive stages EX1 and EX2 with delays 200 ps and 180 ps, giving a six-stage pipeline with the same 20 ps register delay per stage.

One instruction is issued per clock cycle and there are no stalls or hazards. The speedup of the six-stage pipeline over the five-stage pipeline when executing 500 independent instructions is ______ (rounded to two decimal places).

**Answer:** anything from 1.28 to 1.3

**Solution.** **Method: cycle time = slowest stage + register delay; total time = (k + N - 1) cycles.**

*Five-stage pipeline.* Slowest stage EX = 380 ps, so the clock period is $380 + 20 = 400$ ps. Time for $N = 500$ instructions: $(5 + 500 - 1) \times 400 = 504 \times 400 = 201600$ ps.

*Six-stage pipeline.* Stage delays are now 200, 150, 200, 180, 290, 120. The slowest is **MEM at 290 ps**, not EX1. Clock period $290 + 20 = 310$ ps. Time: $(6 + 500 - 1) \times 310 = 505 \times 310 = 156550$ ps.

Speedup $= 201600 / 156550 \approx 1.2878 \approx 1.29$.

**Trap.** After the split it is tempting to take EX1's 200 ps as the new bottleneck, giving a 220 ps clock and a speedup near 1.82. Splitting a stage only helps down to the *next* slowest stage. Ignoring the register delay gives $(504 \times 380)/(505 \times 290) \approx 1.31$, also wrong.

**What was tested:** finding the bottleneck stage after a redesign and charging the register delay to every cycle.

**Remember:** A pipeline's clock period is set by its slowest stage plus the register delay. After splitting the slowest stage, recompute the maximum over all stages: the old second-slowest stage often becomes the new limit.