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Monday26 October 2026

GATE CS & IT · 2027 · Ten questions a day

Past sets26 Oct 2026COA

Pipelining: timing and speedup: GATE CS question with solution

Q.5

A processor's instruction execution is divided into five stages with these delays:

Stage IF ID EX MEM WB
Delay (ps) 200 150 380 290 120

In the pipelined implementation each stage is followed by a pipeline register whose delay of 20 ps adds to the clock period. A designer splits EX into two consecutive stages EX1 and EX2 with delays 200 ps and 180 ps, giving a six-stage pipeline with the same 20 ps register delay per stage.

One instruction is issued per clock cycle and there are no stalls or hazards. The speedup of the six-stage pipeline over the five-stage pipeline when executing 500 independent instructions is ______ (rounded to two decimal places).

One try. It counts in your 26 Oct 2026 set.
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RememberA pipeline's clock period is set by its slowest stage plus the register delay. After splitting the slowest stage, recompute the maximum over all stages: the old second-slowest stage often becomes the new limit.

Solution NAT · 2 marks · no negative marking

Answer: 1.28 to 1.3

Method: cycle time = slowest stage + register delay; total time = (k + N - 1) cycles.

Five-stage pipeline. Slowest stage EX = 380 ps, so the clock period is ps. Time for instructions: ps.

Six-stage pipeline. Stage delays are now 200, 150, 200, 180, 290, 120. The slowest is MEM at 290 ps, not EX1. Clock period ps. Time: ps.

Speedup .

Trap. After the split it is tempting to take EX1's 200 ps as the new bottleneck, giving a 220 ps clock and a speedup near 1.82. Splitting a stage only helps down to the next slowest stage. Ignoring the register delay gives , also wrong.

What was tested: finding the bottleneck stage after a redesign and charging the register delay to every cycle.

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